Publications

Here is a list of my research papers sorted in reverse chronological order.

1. M. Annavaram, E. Grochowski, and P. Reed. Implications of Device Timing Variability on Full Chip Timing. In Proceedings of the 13th International High-Performance Computer Architecture, pages 37-45, Feb 2007.


2. B. Black, M. Annavaram, N. Brekelbaum, J. DeVale, L. Jiang, G.H. Loh, D. McCauley, P. Morrow, D.W. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. Shen, and C. Webb. Die Stacking (3D) Microarchitecture. In Proceedings of the 39th International Symposium on Microarchitecture, pages 469-479, Dec 2006


3. M. Annavaram, E. Grochowski, J. Shen. Mitigating Amdahl’s Law Through EPI Throttling. In Proceedings of the 32nd International Symposium on Computer Architecture, pages 298-309, June 2005.


4. M. Annavaram, R. Rakvic, M. Polito, J. Bouguet, R. Hankins, B. Davies. The Fuzzy Correlation between Code and Performance Predictability. In Proceedings of the 37th International Symposium on Microarchitecture, pages 93-104, Dec 2004.


5. R. Hankins, M. Annavaram, B. Hirano, J. Patel and J. Shen. Comparing OLTP Scaling Behavior on Intel® XeonÔ and Itanium® 2 Processors. In the seventh Workshop on Computer Architecture Evaluation using Commercial Workloads, Feb 2004.


6. M. Annavaram, J. M. Patel and E. S. Davidson. Call Graph Prefetching for Database Applications. ACM Transactions on Computer Systems, 21(4), pages 412-444, Nov 2003.


7. R. Hankins, T. Diep, M. Annavaram, B. Hirano, H. Eri, H. Nueckel, and J. Shen. Scaling and Characterizing Database Workloads: Bridging the Gap between Research and Practice. In Proceedings of the 36th International Symposium on Microarchitecture, pages 151-162, Dec 2003.


8. P. Kundu, M. Annavaram, T. Diep and J. Shen. A Case for Shared Instruction Cache on Chip Multiprocessors Running OLTP. In the Memory Performance: Dealing With Applications, Systems and Architectures Workshop, Sep 2003.


9. T. Diep, M. Annavaram, B. Hirano and J. Shen. Analyzing Performance Characteristics of OLTP Cached Workloads by Linear Interpolation. In the sixth Workshop on Computer Architecture Evaluation using Commercial Workloads, Feb 2003.


10. J. Rupley II, M. Annavaram, J. DeVale, T. Diep and B. Black. Comparing and Contrasting a Commercial OLTP Workload with CPU2000 on IPF. In the fifth Workshop on Workload Characterization, Nov 2002.


11. R. Rakvic, E. Grochowski, B. Black, M. Annavaram, T. Diep and J. Shen. Performance Advantage of the Register Stack in Intel Itanium Processors. In the second Workshop on Explicitly Parallel Instruction Computing Architecture and Compilers, Nov 2002.


12. M. Annavaram, T. Diep and J. Shen. Branch Behavior of a Commercial OLTP Workload on Intel IA32 Processors. In Proceedings of the International Conference on Computer Design, pages 242-248, Sept 2002.


13. M. Annavaram, J. M. Patel and E. S. Davidson. Data Prefetching by Dependence Graph Precomputation. In Proceeding of the 28th International Symposium on Computer Architecture, pages 52-61, July 2001.


14. M. Annavaram, J. M. Patel and E. S. Davidson. Call Graph Prefetching for Database Applications. In Proceedings of the Seventh International High-Performance Computer Architecture, pages 281-290, Jan 2001.


15. M. Annavaram, G. S. Tyson and E. S. Davidson. Instruction Overhead and Data Locality Effects in Superscalar Processors. In Proceedings of the International Symposium on Performance Analysis of Systems and Software, pages 95-100, April 2000.


16. M. Annavaram, W. Najjar. Comparison of Two Storage Models in Data-Driven Multithreaded Architectures. In proceedings of the Symposium on Parallel Distributed Computing, pages 100-110, October 1996.

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